The present application relates to semiconductor devices, and more particularly to lateral devices which are capable of switching relatively high voltages, e.g. of 50V or more.
Many power devices are designed as vertical devices, where the direction of carrier flow is into the semiconductor material (normal to the surface of the wafer). However, there are many advantages to “lateral” power devices, i.e. to transistors which have their direction of carrier flow approximately parallel to the surface. One outstanding attraction of lateral devices is process compatibility, since lateral devices can usually be fabricated with process steps which are the similar to or at least compatible with those used for low-voltage devices. Another attraction is that lateral devices tend to be somewhat easier to integrate with low-voltage devices, to provide “smart power” or “integrated power” functionality.
A MOS-gated transistor referred to as an “oxide-bypassed” VDMOS transistor has been proposed for minimizing the specific on-resistance of devices. See Liang et al., “Oxide-Bypassed VDMOS (OBVDMOS): An Alternative to Superjunction High Voltage MOS Power Devices, 22 IEEE Electron Device Letters No. 8, August 2001, which is hereby incorporated by reference.
The structure shown in FIG. 1 was originally proposed, but several variations of this structure have been suggested. See e.g. Liang et al., “Tunable Oxide-Bypassed VDMOS (OBVDMOS): Breaking the Silicon Limit for the Second Generation”, ISPSD 2002; and Yang et al., “Tunable Oxide-Bypassed Trench Gate MOSFET: Breaking the Ideal Superjunction MOSFET Performance Line at Equal Column Width”, 24 IEEE Electron Device Letters No. 11, November 2003; both of which are hereby incorporated by reference. In the OBVDMOS device shown in FIG. 1, the thick oxide 102 is capable of sustaining the high source-to-drain voltage (between source 120 and drain 130), while the buried pillars 110 of N+ or P+ polysilicon that are located on both sides of the voltage-withstand region 140 help to deplete the voltage-withstand region 140 of n-type carriers when there is a drain-to-source voltage present. For a specific voltage-withstand region width and doping concentration, the thickness of the oxide layer 102 between the N+ or P+ polysilicon 110 and the voltage-withstand region 140 can be selected to deplete the entire voltage-withstand region 140 at peak reverse bias.